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SoC FPGA Interface Development

Design of Interfaces between the FPGA Soft-IP, (HPS / PS) Hard-IP on the Hardware and Software side in any matter.

Experienced FPGA Soft- and Hard-IP Interfaces

  • Low Speed Hard-IP (e.g. SPI, CAN,...)
  • PCIe Hard-IP for PCIe Root-Complex End-Points (e.g. for FPGA PCIe Accelerator Cards)
  • FPGA Transceiver Design (e.g. SFP+ 10Gbit Ethernet Interfaces)
  • FPGA and HPS/PS Shared-memory SDRAM (DDR3, DDR4) Design
    with memory Optimization (SDRAM Calibration, SDRAM pre-loading, SDRAM Bank Interleaving, ...)
  • Tightly Coupled Memory (TCM) Interfaces
  • Soft-IP Interface Development with Arm® AMBA® AXI or Intel® Avalon® Bus Interfaces

Used Design and Verification Tools and Technologies

  • SystemVerilog, VHDL
  • Intel® Quartus® Prime
  • MentorGraphics® (Siemens® EDA) ModelSim™
  • cocotb (for Python-based Testbench Design and Simulation)
  • TCL- and Python-Scripts (for system verification, build automation,...)
  • MathWorks® MATLAB™ (for Simulation input file generation)
  • Arm® Development Studio (DS-5)
  • HDL Soft-IP Timing Analyzation

Used FPGA Device Families

  • Intel® Cyclone® V GX FPGA Family
  • Intel® Cyclone® V SE/SX/ST SoC FPGA Family
  • Intel® Arria® 10 SX SoC FPGA Family
  • Intel® Agilex™ 7 F-Series SoC FPGA